How to Build an XOR Gate Using Only NAND Gates
When you first hear that a NAND gate can replace any other logic gate, the idea feels almost magical. Yet the proof is delightfully simple: by wiring a handful of NAND gates together you can mimic the behavior of an XOR gate—a cornerstone of digital arithmetic and error‑checking circuits. In this guide we’ll walk through the reasoning, the truth tables, and the exact wiring needed for a reliable XOR gate design with NAND gates.
Why NAND Gates Are Universal
The universality of NAND stems from two facts. First, a NAND gate can be configured as a NOT gate by tying its inputs together; the output will be the logical complement of the input. Second, by feeding the output of one NAND into another you can recreate AND and OR functions. Because any Boolean expression can be broken down into combinations of NOT, AND, and OR, a network of NAND gates can implement any desired logic, including the exclusive‑OR operation.
Understanding the XOR Truth Table
Before diving into the circuit, it helps to revisit the XOR truth table. An XOR (exclusive‑OR) gate produces a high output only when its two inputs differ:
- A = 0, B = 0 → Output = 0
- A = 0, B = 1 → Output = 1
- A = 1, B = 0 → Output = 1
- A = 1, B = 1 → Output = 0
From this table we can derive the Boolean expression Y = (A AND ¬B) OR (¬A AND B). The challenge is to replace each AND, OR, and NOT with NAND equivalents.
Step‑by‑Step NAND Implementation
Follow these five stages to translate the expression into a NAND‑only network.
- Generate the NOT signals. Connect inputs A and B to separate NAND gates with both inputs tied together. The outputs become ¬A and ¬B.
- Form the two AND terms. Use NAND gates to combine A with ¬B, and ¬A with B. Remember that a NAND output is the inverse of an AND, so we’ll need to invert the result again later.
- Invert the AND results. Feed each of the previous NAND outputs into a second NAND gate (tied inputs) to obtain the true AND values: A·¬B and ¬A·B.
- Combine the AND terms with an OR. An OR can be built from NAND by applying De Morgan’s law: X OR Y = ¬(¬X AND ¬Y). So first NAND the two AND results together, then invert the outcome with another tied‑input NAND.
- Resulting XOR output. The final output from step 4 is the desired XOR signal, matching the original truth table.
The entire construction uses eight NAND gates: two for the NOT stage, four for the two AND terms (including their inversions), and two for the final OR.
Putting It All Together: Wiring Diagram Description
Imagine a breadboard layout where the leftmost two NAND gates each receive A or B on both inputs, giving you ¬A and ¬B on the right side. Below them, two more NAND gates take A and ¬B, then ¬A and B, producing intermediate signals that are still inverted. These intermediate lines feed into two more NAND gates, each acting as a NOT to restore the proper AND results. Finally, the two true AND outputs converge on a NAND gate; its output passes through one last tied‑input NAND to yield the XOR.
Labeling each gate (N1 through N8) and tracing the wires on paper helps avoid confusion. If you prefer a visual reference, many textbooks illustrate the same eight‑gate arrangement with clear node names; simply map those nodes to your physical connections.
Testing and Troubleshooting Tips
After soldering or wiring the circuit, use a simple two‑switch setup to apply all four input combinations. A handheld LED or a logic probe on the output should light only for the 01 and 10 cases. If the LED stays on for 00 or 11, double‑check the following:
- Inputs tied together on the NOT gates are truly the same line.
- No stray wires are causing a short between A and B.
- All NAND gates receive clean power (typically 5 V for TTL, 3.3 V for CMOS).
Often a miswired inversion step is the culprit; re‑examining the truth table alongside your wiring diagram can quickly reveal the mistake.
Why Build XOR with NAND in the First Place?
Beyond the academic curiosity, there are practical reasons to prefer NAND‑only designs. In some legacy or cost‑sensitive hardware, only NAND chips may be stocked, making a single‑type inventory easier to manage. Additionally, NAND gates tend to have faster switching times than dedicated XOR chips in certain families, which can be advantageous in high‑speed counters or parity generators.
Extending the Concept
Once you’ve mastered the eight‑gate XOR, scaling up is straightforward. A three‑input XOR, for example, can be built by cascading two two‑input XORs—each of which you already know how to construct with NANDs. This modular approach keeps the design tidy and reuses the same building blocks.
FAQ
Can I use a single NAND gate to approximate an XOR?
No. A single NAND cannot produce the exclusive‑OR truth table; at least eight NAND gates are required for an exact implementation.
Are there alternative gate‑level implementations that use fewer components?
Yes. Using a combination of NAND and NOR gates, or employing dedicated XOR ICs, can reduce part count, but the pure NAND solution remains valuable for universality and inventory simplicity.
What voltage levels are safe for typical NAND ICs?
Standard TTL NAND chips operate comfortably at 5 V, while CMOS versions usually accept 3.3 V to 5 V. Always consult the datasheet for the specific part you’re using.
Is the eight‑gate XOR suitable for high‑frequency applications?
Generally, yes. NAND gates often have lower propagation delay than XOR gates, so a well‑routed NAND‑only XOR can perform well in moderate‑speed circuits. For ultra‑high frequencies, consider specialized XOR serializers.